681 search results - page 113 / 137 » Architecture and Implementation of PIM m |
ICDCS
1999
IEEE
14 years 28 days ago
1999
IEEE
In this paper, we describe the design and implementation of an integrated architecture for cache systems that scale to hundreds or thousands of caches with thousands to millions o...
ASYNC
1998
IEEE
14 years 27 days ago
1998
IEEE
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...
FMCAD
1998
Springer
14 years 26 days ago
1998
Springer
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
ISSS
1996
IEEE
14 years 24 days ago
1996
IEEE
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
APPT
2009
Springer
14 years 19 days ago
2009
Springer
Abstract. In many-core CMP architectures, the cache coherence protocol is a key component since it can add requirements of area and power consumption to the final design and, there...