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DAC
1999
ACM
14 years 2 months ago
Dynamically Reconfigurable Architecture for Image Processor Applications
This work presents an overview of the principles that underlie the speed-up achievable by dynamic hardware reconfiguration, proposes a more precise taxonomy for the execution mode...
Alexandro M. S. Adário, Eduardo L. Roehe, S...
IPPS
1998
IEEE
14 years 2 months ago
Evaluation of a Low-Power Reconfigurable DSP Architecture
Abstract. Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an archit...
Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marl...
VLSID
1994
IEEE
113views VLSI» more  VLSID 1994»
14 years 2 months ago
A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs
In this paper, we propose an architecture synthesis methodolog `to realize cascaded Infinite Impulse Response (IIRJfilter in Table Look Up (TLU) Field Progmmmable Gate A m y s (FP...
G. N. Rathna, S. K. Nandy, K. Parthasarathy
CSMR
1999
IEEE
14 years 2 months ago
Architecture Comprehension Tools for a PBX System
The comprehension of the dynamic and static structure of a system is of main importance for purposes of adding features, bug solving, and for redesign activities. This holds parti...
René L. Krikhaar, Loe M. G. Feijs, Roel de ...
MOBISYS
2004
ACM
14 years 9 months ago
Implementing Software on Resource-Constrained Mobile Sensors: Experiences with Impala and ZebraNet
ZebraNet is a mobile, wireless sensor network in which nodes move throughout an environment working to gather and process information about their surroundings [10]. As in many sen...
Ting Liu, Christopher M. Sadler, Pei Zhang, Margar...