6 search results - page 1 / 2 » Architecture and synthesis for multi-cycle on-chip communica... |
ICCAD
2003
IEEE
14 years 7 months ago
2003
IEEE
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration o...
IESS
2007
Springer
14 years 5 months ago
2007
Springer
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
ICCD
2006
IEEE
14 years 7 months ago
2006
IEEE
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
DAC
2001
ACM
14 years 11 months ago
2001
ACM
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
VLSID
2002
IEEE
14 years 11 months ago
2002
IEEE
: In this paper, we present a point-to-point (P2P) communication synthesis methodology for SystemOn-Chip (SOC) design. We consider real-time systems where IP selection, mapping and...