Sciweavers

260 search results - page 29 / 52
» Array SSA Form and Its Use in Parallelization
Sort
View
IPPS
2006
IEEE
14 years 1 months ago
An optimal architecture for a DDC
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Sm...
IROS
2007
IEEE
91views Robotics» more  IROS 2007»
14 years 1 months ago
A dynamic single actuator vertical climbing robot
— A climbing robot mechanism is introduced, which uses dynamic movements to climb between two parallel vertical walls. This robot relies on its own internal dynamic motions to ga...
Amir Degani, Amir Shapiro, Howie Choset, Matthew T...
ICS
1989
Tsinghua U.
13 years 11 months ago
Convergence rate and termination of asynchronous iterative algorithms
We consider iterative algorithms of the form z := f(z), executed by a parallel or distributed computing system. We focus on asynchronous implementations whereby each processor ite...
Dimitri P. Bertsekas, John N. Tsitsiklis
ICPP
2002
IEEE
14 years 14 days ago
Software Caching using Dynamic Binary Rewriting for Embedded Devices
A software cache implements instruction and data caching entirely in software. Dynamic binary rewriting offers a means to specialize the software cache miss checks at cache miss t...
Chad Huneycutt, Joshua B. Fryman, Kenneth M. Macke...
IPPS
2007
IEEE
14 years 1 months ago
Automatic Trace-Based Performance Analysis of Metacomputing Applications
The processing power and memory capacity of independent and heterogeneous parallel machines can be combined to form a single parallel system that is more powerful than any of its ...
Daniel Becker, Felix Wolf, Wolfgang Frings, Markus...