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ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 6 months ago
Soft error reduction in combinational logic using gate resizing and flipflop selection
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
Rajeev R. Rao, David Blaauw, Dennis Sylvester
DAC
2009
ACM
14 years 4 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
SC
2009
ACM
14 years 4 months ago
Age based scheduling for asymmetric multiprocessors
Asymmetric (or Heterogeneous) Multiprocessors are becoming popular in the current era of multi-cores due to their power efficiency and potential performance and energy efficienc...
Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim
WSDM
2009
ACM
191views Data Mining» more  WSDM 2009»
14 years 4 months ago
Generating labels from clicks
The ranking function used by search engines to order results is learned from labeled training data. Each training point is a (query, URL) pair that is labeled by a human judge who...
Rakesh Agrawal, Alan Halverson, Krishnaram Kenthap...
HIPEAC
2009
Springer
14 years 4 months ago
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors
Process variations, which lead to timing and power variations across identically-designed components, have been identified as one of the key future design challenges by the semico...
Yang Ding, Mahmut T. Kandemir, Mary Jane Irwin, Pa...