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SBCCI
2006
ACM
126views VLSI» more  SBCCI 2006»
14 years 1 months ago
Power constrained design optimization of analog circuits based on physical gm/ID characteristics
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
Alessandro Girardi, Sergio Bampi
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
14 years 21 days ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell
CGI
2000
IEEE
14 years 6 days ago
Dynamic 3D Maps and Their Texture-Based Design
Three-dimensional maps are fundamental tools for presenting, exploring, and manipulating geo data. This paper describes multiresolution concepts for 3D maps and their texture-base...
Jürgen Döllner, Klaus Hinrichs
DAC
2007
ACM
14 years 8 months ago
Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design
This work is motivated by the strong demand of reliability enhancement over flash memory. Our objective is to improve the endurance of flash memory with limited overhead and witho...
Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo
DAC
2001
ACM
14 years 8 months ago
Speculation Techniques for High Level Synthesis of Control Intensive Designs
The quality of synthesis results for most high level synthesis approaches is strongly a ected by the choice of control ow through conditions and loops in the input description. In...
Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dut...