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121
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DAC
2005
ACM
15 years 4 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
342
Voted
DAC
2012
ACM
13 years 4 months ago
Equivalence checking for behaviorally synthesized pipelines
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
Kecheng Hao, Sandip Ray, Fei Xie
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
15 years 11 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
SP
2010
IEEE
140views Security Privacy» more  SP 2010»
15 years 6 months ago
Inspector Gadget: Automated Extraction of Proprietary Gadgets from Malware Binaries
Abstract—Unfortunately, malicious software is still an unsolved problem and a major threat on the Internet. An important component in the fight against malicious software is the...
Clemens Kolbitsch, Thorsten Holz, Christopher Krue...
115
Voted
ICDCS
2003
IEEE
15 years 7 months ago
Compiler Scheduling of Mobile Agents for Minimizing Overheads
Mobile code carried by a mobile agent can automatically travel to several data sources in order to complete a designated program. Traditionally, most mobile agent systems [7][8][1...
Xiaotong Zhuang, Santosh Pande