333 search results - page 23 / 67 » Automatic Generation of Parallel Treebanks |
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
HPDC
2005
IEEE
14 years 1 months ago
2005
IEEE
good data partitioning scheme is the need of the time. However it is very diflcult to arrive at a good solution as the number of possible dutupartitionsfor a given real lifeprogra...
SCOPES
2004
Springer
14 years 27 days ago
2004
Springer
Digital signal processing applications are implemented in embedded systems with fixed-point arithmetic to minimize the cost and the power consumption. To reduce the application ti...
IPPS
2003
IEEE
14 years 25 days ago
2003
IEEE
To understand the performance of modern Java systems one must observe execution in the context of specific architectures. It is also important that we make these observations usi...
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...