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» Automatic On-chip Memory Minimization for Data Reuse
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IESS
2007
Springer
165views Hardware» more  IESS 2007»
14 years 5 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
FCCM
2007
IEEE
129views VLSI» more  FCCM 2007»
14 years 5 months ago
Automatic On-chip Memory Minimization for Data Reuse
FPGA-based computing engines have become a promising option for the implementation of computationally intensive applications due to high flexibility and parallelism. However, one...
Qiang Liu, George A. Constantinides, Konstantinos ...
ASPDAC
2006
ACM
105views Hardware» more  ASPDAC 2006»
14 years 5 months ago
Maximizing data reuse for minimizing memory space requirements and execution cycles
Mahmut T. Kandemir, Guangyu Chen, Feihui Li
ISCAS
2006
IEEE
96views Hardware» more  ISCAS 2006»
14 years 5 months ago
Frame-level data reuse for motion-compensated temporal filtering
— Motion-compensated temporal filtering (MCTF) is an open-loop prediction scheme, so the frame-level data reuse for MCTF is possible. In this paper, we propose two general frame...
Ching-Yeh Chen, Yi-Hau Chen, Chih-Chi Cheng, Liang...
CODES
2010
IEEE
13 years 8 months ago
Automatic memory partitioning: increasing memory parallelism via data structure partitioning
In high-level synthesis, pipelined designs are often restricted by the number of memory banks available to the synthesis system. Using multiple memory banks can improve the perfor...
Yosi Ben-Asher, Nadav Rotem