79 search results - page 12 / 16 » Automatic Profile Generation in eRACE |
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
DGO
2004
13 years 9 months ago
2004
The focus of this paper reports a collaborative effort with the State of New Jersey in designing and building a human-centered e-government portal to support small and medium size...
DMDW
2003
13 years 9 months ago
2003
Data Warehouse-(DW) logical design often start with a conceptual schema and then generates relational structures. Applying this approach implies to cope with two main aspects: (i) ...
AIPS
2009
13 years 8 months ago
2009
Recently, Helmert and Geffner proposed the context-enhanced additive heuristic, where fact costs are evaluated relative to context states that arise from achieving first a pivot c...
ENTCS
2008
13 years 7 months ago
2008
A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network mu...