95 search results - page 10 / 19 » Automatic abstraction and verification of verilog models |
TCAD
2008
13 years 7 months ago
2008
The verification of a system-on-chip is challenging due to its high level of integration. Multiple components in a system can behave concurrently and compete for resources. Hence, ...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Abstract-- The PPV is a robust phase domain macromodel for oscillators. It has been proven to predict oscillators' responses correctly under small signal perturbations, and ca...
ICFEM
2009
Springer
13 years 5 months ago
2009
Springer
Abstract. This paper shows how Ptolemy II discrete-event (DE) models can be formally analyzed using Real-Time Maude. We formalize in Real-Time Maude the semantics of a subset of hi...
ECCB
2008
IEEE
13 years 7 months ago
2008
IEEE
Abstract: Models of the dynamics of cellular interaction networks have become increasingly larger in recent years. Formal verification based on model checking provides a powerful t...
FDL
2004
IEEE
13 years 11 months ago
2004
IEEE
gn process of embedded systems moves currently towards higher levels of abstraction. As a consequence, a need arises for an early and realistic assessment of system level design d...