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» Automatic abstraction and verification of verilog models
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FMICS
2010
Springer
13 years 7 months ago
Correctness of Sensor Network Applications by Software Bounded Model Checking
We investigate the application of the software bounded model checking tool CBMC to the domain of wireless sensor networks (WSNs). We automatically generate a software behavior mode...
Frank Werner, David Faragó
CIBSE
2008
ACM
13 years 9 months ago
Using Refinement Checking as System Testing
Abstract. Software testing is an expensive and time-consuming activity; it is also error-prone due to human factors. But, it still is the most common effort used in the software in...
Cristiano Bertolini, Alexandre Mota
ICSE
2004
IEEE-ACM
14 years 7 months ago
Assume-Guarantee Verification of Source Code with Design-Level Assumptions
Model checking is an automated technique that can be used to determine whether a system satisfies certain required properties. To address the "state explosion" problem a...
Dimitra Giannakopoulou, Corina S. Pasareanu, Jamie...
FUIN
2006
142views more  FUIN 2006»
13 years 7 months ago
Comparing BDD and SAT Based Techniques for Model Checking Chaum's Dining Cryptographers Protocol
Abstract. We analyse different versions of the Dining Cryptographers protocol by means of automatic verification via model checking. Specifically we model the protocol in terms of ...
Magdalena Kacprzak, Alessio Lomuscio, Artur Niewia...
EMSOFT
2008
Springer
13 years 9 months ago
Automatically transforming and relating Uppaal models of embedded systems
Relations between models are important for effective automatic validation, for comparing implementations with specifications, and for increased understanding of embedded systems d...
Timothy Bourke, Arcot Sowmya