Sciweavers

95 search results - page 12 / 19
» Automatic abstraction and verification of verilog models
Sort
View
CAV
2006
Springer
133views Hardware» more  CAV 2006»
13 years 11 months ago
Programs with Lists Are Counter Automata
Abstract. We address the verification problem of programs manipulating oneselector linked data structures. We propose a new automated approach for checking safety and termination f...
Ahmed Bouajjani, Marius Bozga, Peter Habermehl, Ra...
HASE
2008
IEEE
13 years 7 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri
TACAS
2010
Springer
170views Algorithms» more  TACAS 2010»
13 years 5 months ago
SLAB: A Certifying Model Checker for Infinite-State Concurrent Systems
Systems and protocols combining concurrency and infinite state space occur quite often in practice, but are very difficult to verify automatically. At the same time, if the system ...
Klaus Dräger, Andrey Kupriyanov, Bernd Finkbe...
CAV
2009
Springer
209views Hardware» more  CAV 2009»
14 years 7 months ago
Static and Precise Detection of Concurrency Errors in Systems Code Using SMT Solvers
Context-bounded analysis is an attractive approach to verification of concurrent programs. Bounding the number of contexts executed per thread not only reduces the asymptotic compl...
Shuvendu K. Lahiri, Shaz Qadeer, Zvonimir Rakamari...
FMICS
2010
Springer
13 years 8 months ago
SMT-Based Formal Verification of a TTEthernet Synchronization Function
Abstract. TTEthernet is a communication infrastructure for mixedcriticality systems that integrates dataflow from applications with different criticality levels on a single network...
Wilfried Steiner, Bruno Dutertre