95 search results - page 16 / 19 » Automatic abstraction and verification of verilog models |
DLT
2009
13 years 5 months ago
2009
Abstract. Temporal logics are a well investigated formalism for the specification and verification of reactive systems. Using formal verification techniques, we can ensure the corr...
ICST
2009
IEEE
13 years 5 months ago
2009
IEEE
Bounded model checking--as well as symbolic equivalence checking--are highly successful techniques in the hardware domain. Recently, bit-vector bounded model checkers like CBMC ha...
FM
2009
Springer
13 years 5 months ago
2009
Springer
Abstract. We propose an approach to automatic verification of realtime systems against scenario-based requirements. A real-time system is modeled as a network of Timed Automata (TA...
IGPL
2006
13 years 7 months ago
2006
Abstract. This paper addresses the problem of establishing temporal properties of programs written in languages, such as Java, that make extensive use of the heap to allocate-and d...
ADBIS
2006
Springer
13 years 11 months ago
2006
Springer
Among the most important expected benefits of a global service oriented architecture leveraging web service standards is an increased level of automation in the discovery, composit...