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HPCA
2002
IEEE
14 years 17 days ago
Non-Vital Loads
As the frequency gap between main memory and modern microprocessor grows, the implementation and efficiency of on-chip caches become more important. The growing latency to memory ...
Ryan Rakvic, Bryan Black, Deepak Limaye, John Paul...
IPPS
2008
IEEE
14 years 2 months ago
CoSL: A coordinated statistical learning approach to measuring the capacity of multi-tier websites
Website capacity determination is crucial to measurement-based access control, because it determines when to turn away excessive client requests to guarantee consistent service qu...
Jia Rao, Cheng-Zhong Xu
IPPS
2007
IEEE
14 years 1 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
SPAA
2004
ACM
14 years 1 months ago
DCAS is not a silver bullet for nonblocking algorithm design
Despite years of research, the design of efficient nonblocking algorithms remains difficult. A key reason is that current shared-memory multiprocessor architectures support only s...
Simon Doherty, David Detlefs, Lindsay Groves, Chri...
IEEEPACT
2002
IEEE
14 years 16 days ago
Using the Compiler to Improve Cache Replacement Decisions
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosen...