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IPPS
2000
IEEE
13 years 12 months ago
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
ICPP
1999
IEEE
13 years 12 months ago
Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors
On-line transaction processing exhibits poor memory behavior in high-end multiprocessor servers because of complex sharing patterns and substantial interaction between the databas...
Jim Nilsson, Fredrik Dahlgren
ICS
1997
Tsinghua U.
13 years 11 months ago
Eliminating Cache Conflict Misses through XOR-Based Placement Functions
This paper makes the case for the use of XOR-based placement functions for cache memories. It shows that these XOR-mapping schemes can eliminate many conflict misses for direct-ma...
Antonio González, Mateo Valero, Nigel P. To...
CCGRID
2004
IEEE
13 years 11 months ago
Unifier: unifying cache management and communication buffer management for PVFS over InfiniBand
The advent of networking technologies and high performance transport protocols facilitates the service of storage over networks. However, they pose challenges in integration and i...
Jiesheng Wu, Pete Wyckoff, Dhabaleswar K. Panda, R...
CCGRID
2010
IEEE
13 years 8 months ago
A Map-Reduce System with an Alternate API for Multi-core Environments
Map-reduce framework has received a significant attention and is being used for programming both large-scale clusters and multi-core systems. While the high productivity aspect of ...
Wei Jiang, Vignesh T. Ravi, Gagan Agrawal