237 search results - page 43 / 48 » Automating Refinement Checking in Probabilistic System Desig... |
CADE
2007
Springer
14 years 7 months ago
2007
Springer
Abstract. First order logic provides a convenient formalism for describing a wide variety of verification conditions. Two main approaches to checking such conditions are pure first...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
We discover significant value-dependent programming energy variations in multi-level cell (MLC) flash memories, and introduce an energy-aware data compression method that minimize...
UML
2005
Springer
14 years 1 months ago
2005
Springer
We present in this paper a rigorous and automated based approach for the behavioral validation of control software systems. This approach relies on metamodeling, model-transformati...
SIGSOFT
2007
ACM
14 years 8 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
CORR
2007
Springer
13 years 7 months ago
2007
Springer
This paper deals with a common verification methodology and environment for SystemC BCA and RTL models. The aim is to save effort by avoiding the same work done twice by different...