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CONCUR
2006
Springer
13 years 11 months ago
Sanity Checks in Formal Verification
One of the advantages of temporal-logic model-checking tools is their ability to accompany a negative answer to the correctness query by a counterexample to the satisfaction of the...
Orna Kupferman
SNPD
2008
13 years 9 months ago
Towards Formal Modeling and Analysis of Networks of Embedded Medical Devices in Real-Time Maude
With the increasing number of medical devices and of accidents resulting from them being used in isolation in a hectic operating room, there is a trend towards integrating such de...
Peter Csaba Ölveczky
IPL
2008
102views more  IPL 2008»
13 years 7 months ago
The connection between two ways of reasoning about partial functions
Undefined terms involving the application of partial functions and operators are common in program specifications and in discharging proof obligations that arise in design. One wa...
John S. Fitzgerald, Cliff B. Jones
SIGSOFT
2005
ACM
14 years 8 months ago
Reasoning about confidentiality at requirements engineering time
Growing attention is being paid to application security at requirements engineering time. Confidentiality is a particular subclass of security concerns that requires sensitive inf...
Renaud De Landtsheer, Axel van Lamsweerde
COMPSAC
2007
IEEE
13 years 11 months ago
Unified Property Specification for Hardware/Software Co-Verification
Hardware/software co-verification is becoming an indispensable tool for building highly trustworthy embedded systems. A stumbling block to effective co-verification using model ch...
Fei Xie, Huaiyu Liu