233 search results - page 43 / 47 » Balance Testing of Logic Circuits |
SLIP
2005
ACM
14 years 2 months ago
2005
ACM
We propose in this paper a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two ...
ASPDAC
2008
ACM
13 years 10 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
IJCNN
2000
IEEE
14 years 29 days ago
2000
IEEE
This paper shows an application in the field of Electronic CAD of the Selfish Gene algorithm, an evolutionary algorithm based on a recent interpretation of the Darwinian theory. Te...
CIIA
2009
13 years 9 months ago
2009
In this paper, we present a new synthesis feature namely, "Xor matching", and the foldback product term synthesis for Complex Programmable Logic Devices (CPLD) architectu...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
— There is a growing interest in developing low cost, low power, highly integrated biosensor systems to characterize individual cells for applications such as cell analysis, drug...