31 search results - page 5 / 7 » Balanced Cache: Reducing Conflict Misses of Direct-Mapped Ca... |
MSE
2002
IEEE
14 years 1 months ago
2002
IEEE
This paper presents the study of running several core multimedia applications on a simultaneous multithreading (SMT) architecture and derives design principles for multimedia soft...
HPCA
2000
IEEE
14 years 1 months ago
2000
IEEE
Main memory accesses continue to be a significant bottleneck for applications whose working sets do not fit in second-level caches. With the trend of greater associativity in seco...
TMM
2008
13 years 8 months ago
2008
Abstract--The 2-D Discrete Wavelet Transform (DWT) consumes up to 68% of the JPEG2000 encoding time. In this paper, we develop efficient implementations of this important kernel on...
ISCA
1994
IEEE
14 years 21 days ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
CASES
2001
ACM
14 years 7 days ago
2001
ACM
With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective...