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HPCA
2004
IEEE
14 years 10 months ago
Signature Buffer: Bridging Performance Gap between Registers and Caches
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
Lu Peng, Jih-Kwon Peir, Konrad Lai
MICRO
1997
IEEE
86views Hardware» more  MICRO 1997»
14 years 2 months ago
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction
We revisit memory hierarchy design viewing memory as an inter-operation communication agent. This perspective leads to the development of novel methods of performing inter-operati...
Andreas Moshovos, Gurindar S. Sohi
ICS
2004
Tsinghua U.
14 years 3 months ago
CQoS: a framework for enabling QoS in shared caches of CMP platforms
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
Ravi R. Iyer
MSS
2003
IEEE
151views Hardware» more  MSS 2003»
14 years 3 months ago
Accurate Modeling of Cache Replacement Policies in a Data Grid
Caching techniques have been used to improve the performance gap of storage hierarchies in computing systems. In data intensive applications that access large data files over wid...
Ekow J. Otoo, Arie Shoshani
SODA
2000
ACM
95views Algorithms» more  SODA 2000»
13 years 11 months ago
Towards a theory of cache-efficient algorithms
We present a model that enables us to analyze the running time of an algorithm on a computer with a memory hierarchy with limited associativity, in terms of various cache parameter...
Sandeep Sen, Siddhartha Chatterjee