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RV
2010
Springer
171views Hardware» more  RV 2010»
13 years 5 months ago
Runtime Verification for Software Transactional Memories
Software transactional memories (STMs) promise simple and efficient concurrent programming. Several correctness properties have been proposed for STMs. Based on a bounded conflict ...
Vasu Singh
ACSD
2006
IEEE
118views Hardware» more  ACSD 2006»
14 years 1 months ago
Strategies for Optimised STG Decomposition
— When synthesising an asynchronous circuit from an STG, one often encounters the state explosion problem. In order to alleviate this problem one can decompose the STG into small...
Mark Schäfer, Walter Vogler, Ralf Wollowski, ...
FPL
2008
Springer
153views Hardware» more  FPL 2008»
13 years 9 months ago
Exploring FPGA network on chip implementations across various application and network loads
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...
Graham Schelle, Dirk Grunwald
MICRO
1995
IEEE
108views Hardware» more  MICRO 1995»
13 years 11 months ago
SPAID: software prefetching in pointer- and call-intensive environments
Software prefetching, typically in the context of numericor loop-intensive benchmarks, has been proposed as one remedy for the performance bottleneck imposed on computer systems b...
Mikko H. Lipasti, William J. Schmidt, Steven R. Ku...
FPL
2005
Springer
110views Hardware» more  FPL 2005»
14 years 1 months ago
CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools
Abstract. We propose CUSTARD — CUStomisable Threaded ARchitecture — a soft processor design space that combines support for multiple hardware threads and automatically generate...
Robert G. Dimond, Oskar Mencer, Wayne Luk