436 search results - page 68 / 88 » Benchmarking and hardware implementation of JPEG-LS |
IPPS
2000
IEEE
14 years 1 days ago
2000
IEEE
Parallel simulation techniques are often employed to meet the computational requirements of large hardware simulations in order to reduce simulation time. In addition, partitionin...
ASPLOS
2000
ACM
14 years 1 days ago
2000
ACM
Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effec...
FMCAD
1998
Springer
13 years 12 months ago
1998
Springer
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
HPCA
1996
IEEE
13 years 12 months ago
1996
IEEE
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...