Sciweavers

403 search results - page 25 / 81
» Bits through ARQs
Sort
View
ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
14 years 4 months ago
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Abstract— Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a us...
Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan ...
SBACPAD
2009
IEEE
155views Hardware» more  SBACPAD 2009»
14 years 2 months ago
SPARC16: A New Compression Approach for the SPARC Architecture
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo C...
CODES
2008
IEEE
14 years 1 months ago
Asynchronous transient resilient links for NoC
This paper proposes a new link for asynchronous NoC communications that is resilient to transient faults on the wires of the link without impact on the data transfer capability. R...
Simon Ogg, Bashir M. Al-Hashimi, Alexandre Yakovle...
IPPS
2008
IEEE
14 years 1 months ago
Design of steering vectors for dynamically reconfigurable architectures
An architectural framework is studied that can perform dynamic reconfiguration. A basic objective is to dynamically reconfigure the architecture so that its configuration is well ...
Nick A. Mould, Brian F. Veale, John K. Antonio, Mo...
IPSN
2007
Springer
14 years 1 months ago
Power scheduling for wireless sensor and actuator networks
We previously presented a model for some wireless sensor and actuator network (WSAN) applications based on the vector space tools of frame theory. In this WSAN model there is a we...
Christopher J. Rozell, Don H. Johnson