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ISCA
2012
IEEE
333views Hardware» more  ISCA 2012»
11 years 10 months ago
Reducing memory reference energy with opportunistic virtual caching
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
Arkaprava Basu, Mark D. Hill, Michael M. Swift
JDCTA
2010
113views more  JDCTA 2010»
13 years 2 months ago
A Watermarking Algorithm Based on Block Energy Analysis of Wavelet Transform's Coefficients and Lorenz Chaotic Attractor
Perceptual transparency and robustness are conflicting requirements. To ensure the security of the watermarkhow to choose the embedding position and intensity is a difficult probl...
Xuelong Hu, Wei Tian, Yongai Zheng
RTAS
2006
IEEE
14 years 1 months ago
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
EMSOFT
2010
Springer
13 years 5 months ago
Optimal WCET-aware code selection for scratchpad memory
We propose the first polynomial-time code selection algorithm for minimising the worst-case execution time of a nonnested loop executed on a fully pipelined processor that uses sc...
Hui Wu, Jingling Xue, Sridevan Parameswaran
CASES
2006
ACM
14 years 1 months ago
Mitigating soft error failures for multimedia applications by selective data protection
With advances in process technology, soft errors (SE) are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft ...
Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, N...