Sciweavers

613 search results - page 58 / 123
» Block cache for embedded systems
Sort
View
HPCA
2001
IEEE
14 years 8 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
14 years 1 months ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang
ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
13 years 5 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
ASPDAC
2009
ACM
111views Hardware» more  ASPDAC 2009»
14 years 2 months ago
A UML-based approach for heterogeneous IP integration
- With increasing availability of predefined IP (Intellectual Properties) blocks and inexpensive microprocessors, embedded system designers are faced with more design choices than ...
Zhenxin Sun, Weng-Fai Wong
ASPLOS
2006
ACM
14 years 1 months ago
Geiger: monitoring the buffer cache in a virtual machine environment
Virtualization is increasingly being used to address server management and administration issues like flexible resource allocation, service isolation and workload migration. In a...
Stephen T. Jones, Andrea C. Arpaci-Dusseau, Remzi ...