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RTSS
2008
IEEE
14 years 2 months ago
Symbolic Computation of Schedulability Regions Using Parametric Timed Automata
In this paper, we address the problem of symbolically computing the region in the parameter’s space that guarantees a feasible schedule, given a set of real-time tasks character...
Alessandro Cimatti, Luigi Palopoli, Yusi Ramadian
MTV
2006
IEEE
138views Hardware» more  MTV 2006»
14 years 1 months ago
Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs
In this paper we will present an optimized structural 01X-SAT-solver for bounded model checking of blackbox designs that exploits semantical knowledge regarding the node selection...
Marc Herbstritt, Bernd Becker, Christoph Scholl
FMSD
2006
140views more  FMSD 2006»
13 years 7 months ago
Dealing with practical limitations of distributed timed model checking for timed automata
Two base algorithms are known for reachability verification over timed automata. They are called forward and backwards, and traverse the automata edges using either successors or p...
Víctor A. Braberman, Alfredo Olivero, Ferna...
CAV
2007
Springer
104views Hardware» more  CAV 2007»
14 years 1 months ago
Revamping TVLA: Making Parametric Shape Analysis Competitive
Abstract. TVLA is a parametric framework for shape analysis that can be easily instantiated to create different kinds of analyzers for checking properties of programs that use link...
Igor Bogudlov, Tal Lev-Ami, Thomas W. Reps, Mooly ...
FM
2009
Springer
104views Formal Methods» more  FM 2009»
14 years 2 months ago
A Metric Encoding for Bounded Model Checking
In Bounded Model Checking both the system model and the checked property are translated into a Boolean formula to be analyzed by a SAT-solver. We introduce a new encoding technique...
Matteo Pradella, Angelo Morzenti, Pierluigi San Pi...