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» Bounded Model Checking with QBF
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DAC
2009
ACM
14 years 8 months ago
Computing bounds for fault tolerance using formal techniques
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
André Sülflow, Görschwin Fey, Rol...
CAV
2007
Springer
86views Hardware» more  CAV 2007»
14 years 1 months ago
From Liveness to Promptness
Liveness temporal properties state that something “good” eventually happens, e.g., every request is eventually granted. In Linear Temporal Logic (LTL), there is no a priori bo...
Orna Kupferman, Nir Piterman, Moshe Y. Vardi
KBSE
2007
IEEE
14 years 1 months ago
Sequential circuits for program analysis
A number of researchers have proposed the use of Boolean satisfiability solvers for verifying C programs. They encode correctness checks as Boolean formulas using finitization: ...
Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid
FUIN
2000
115views more  FUIN 2000»
13 years 7 months ago
Constructing the Least Models for Positive Modal Logic Programs
We give algorithms to construct the least L-model for a given positive modal logic program P, where L can be one of the modal logics KD, T, KDB, B, KD4, S4, KD5, KD45, and S5. If L...
Linh Anh Nguyen
ATVA
2008
Springer
144views Hardware» more  ATVA 2008»
13 years 9 months ago
Tests, Proofs and Refinements
1 : Logic in Specification and Verification (abstract) Natarajan Shankar (SRI) Session Chair : Sungdeok Cha 12 : 00 13 : 00 Lunch 13 : 00 15 : 00 2 : Boolean Modeling of Cell Biolo...
Sriram K. Rajamani