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151
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TC
2010
15 years 2 months ago
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pr...
FCCM
2002
IEEE
174views VLSI» more  FCCM 2002»
15 years 9 months ago
PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs
This paper explores the implications of integrating flexible module generation into a compiler for FPGAs. The objective is to improve the programmabilityof FPGAs, or in other wor...
Oskar Mencer
140
Voted
SIGMETRICS
2008
ACM
128views Hardware» more  SIGMETRICS 2008»
15 years 4 months ago
Loss-aware network coding for unicast wireless sessions: design, implementation, and performance evaluation
Local network coding is growing in prominence as a technique to facilitate greater capacity utilization in multi-hop wireless networks. A specific objective of such local network ...
Shravan K. Rayanchu, Sayandeep Sen, Jianming Wu, S...
AHS
2007
IEEE
247views Hardware» more  AHS 2007»
15 years 10 months ago
Hybrid Communication Medium for Adaptive SoC Architectures
This paper proposes a hybrid communication medium for on-chip communication targeting adaptive SoC architectures. Unlike the work carried out in literature, where the term “hybr...
Balal Ahmad, Ali Ahmadinia, Tughrul Arslan
ASPDAC
2008
ACM
134views Hardware» more  ASPDAC 2008»
15 years 6 months ago
Automatic re-coding of reference code into structured and analyzable SoC models
The quality of the input system model has a direct bearing on the effectiveness of the system exploration and synthesis tools. Given a well-structured system model, tools today are...
Pramod Chandraiah, Rainer Dömer