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» C Compiler Design for an Industrial Network Processor
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ICC
2009
IEEE
116views Communications» more  ICC 2009»
13 years 6 months ago
Efficient Implementation of Binary Sequence Generator for WiMAX and WRAN on Programmable Digital Signal Processor
In this paper, an efficient design for implementing binary sequence generator on 32-bit instruction execution mode TI TMS320C6416 DSP is presented. The main goal is to achieve high...
Lok Tiing Tie, Ser Wah Oh, K. J. M. Kua
PEPM
1999
ACM
14 years 21 days ago
Certifying Compilation and Run-Time Code Generation
A certifying compiler takes a source language program and produces object code, as well as a certi cate" that can be used to verify that the object code satis es desirable pr...
Luke Hornof, Trevor Jim
CF
2007
ACM
14 years 13 days ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
INFOCOM
2007
IEEE
14 years 2 months ago
On the Extreme Parallelism Inside Next-Generation Network Processors
Next-generation high-end Network Processors (NP) must address demands from both diversified applications and ever-increasing traffic pressure. One major challenge is to design an e...
Lei Shi, Yue Zhang 0006, Jianming Yu, Bo Xu, Bin L...
NOCS
2007
IEEE
14 years 2 months ago
The Power of Priority: NoC Based Distributed Cache Coherency
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...