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FPL
2005
Springer
140views Hardware» more  FPL 2005»
14 years 3 months ago
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
Usama Malik, Oliver Diessel
FPGA
2004
ACM
120views FPGA» more  FPGA 2004»
14 years 3 months ago
Flexibility measurement of domain-specific reconfigurable hardware
Traditional metrics used to compare hardware designs include area, performance, and power. However, these metrics do not form a complete evaluation of reconfigurable hardware. For...
Katherine Compton, Scott Hauck
FCCM
2004
IEEE
163views VLSI» more  FCCM 2004»
14 years 1 months ago
Implementation Results of Bloom Filters for String Matching
Network Intrusion Detection and Prevention Systems (IDPS) use string matching to scan Internet packets for malicious content. Bloom filters offer a mechanism to search for a large...
Michael Attig, Sarang Dharmapurikar, John W. Lockw...
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
14 years 6 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
FPGA
2009
ACM
188views FPGA» more  FPGA 2009»
14 years 4 months ago
Clock power reduction for virtex-5 FPGAs
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Qiang Wang, Subodh Gupta, Jason Helge Anderson