869 search results - page 158 / 174 » Cache Architectures for Reconfigurable Hardware |
DSN
2003
IEEE
14 years 23 days ago
2003
IEEE
The DepAuDE architecture provides middleware to integrate fault tolerance support into distributed embedded automation applications. It allows error recovery to be expressed in te...
DASIP
2010
13 years 2 months ago
2010
Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++...
WCE
2007
13 years 8 months ago
2007
- Machine vision has evolved to become a mainstream automation tool, enabling computers to replace human vision in high speed and precision manufacturing techniques. Images usually...
FPGA
2004
ACM
13 years 11 months ago
2004
ACM
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
LCTRTS
1999
Springer
13 years 11 months ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...