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» Cache Hierarchy and Memory Subsystem of the AMD Opteron Proc...
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MICRO
2010
IEEE
333views Hardware» more  MICRO 2010»
13 years 5 months ago
Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor
Pat Conway, Nathan Kalyanasundharam, Gregg Donley,...
IWNAS
2008
IEEE
14 years 1 months ago
Software Barrier Performance on Dual Quad-Core Opterons
Multi-core processors based SMP servers have become building blocks for Linux clusters in recent years because they can deliver better performance for multi-threaded programs thro...
Jie Chen, William A. Watson III
IPCCC
2007
IEEE
14 years 1 months ago
Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study
As Chip Multiprocessor (CMP) has become the mainstream in processor architectures, Intel and AMD have introduced their dual-core processors to the PC market. In this paper, perfor...
Lu Peng, Jih-Kwon Peir, Tribuvan K. Prakash, Yen-K...
ASPLOS
2008
ACM
13 years 9 months ago
Accelerating two-dimensional page walks for virtualized systems
Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. Nested paging complements existing page walk hardwar...
Ravi Bhargava, Ben Serebrin, Francesco Spadini, Sr...
CORR
2011
Springer
177views Education» more  CORR 2011»
13 years 2 months ago
Measuring NUMA effects with the STREAM benchmark
Modern high-end machines feature multiple processor packages, each of which contains multiple independent cores and integrated memory controllers connected directly to dedicated ph...
Lars Bergstrom