13 search results - page 2 / 3 » Cache Hierarchy and Memory Subsystem of the AMD Opteron Proc... |
ACMMSP
2006
ACM
14 years 1 months ago
2006
ACM
Stencil-based kernels constitute the core of many scientific applications on block-structured grids. Unfortunately, these codes achieve a low fraction of peak performance, due pr...
HPCC
2005
Springer
14 years 28 days ago
2005
Springer
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
SBACPAD
2003
IEEE
14 years 21 days ago
2003
IEEE
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, prog...
ISCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-c...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
The trend of increasing speed and complexity in the single-core processor as stated in the Moore’s law is facing practical challenges. As a result, the multi-core processor arch...