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DSD
2003
IEEE
107views Hardware» more  DSD 2003»
14 years 1 months ago
DYNORA: A New Caching Technique
Cache design for high performance computing requires the realization of two seemingly disjoint goals of higher hit ratios at reduced access times. Recent research advocates the us...
P. Srivatsan, P. B. Sudarshan, P. P. Bhaskaran
IEEEPACT
2002
IEEE
14 years 1 months ago
Using the Compiler to Improve Cache Replacement Decisions
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosen...
VLDB
2005
ACM
180views Database» more  VLDB 2005»
14 years 1 months ago
Cache-conscious Frequent Pattern Mining on a Modern Processor
In this paper, we examine the performance of frequent pattern mining algorithms on a modern processor. A detailed performance study reveals that even the best frequent pattern min...
Amol Ghoting, Gregory Buehrer, Srinivasan Parthasa...
CC
2003
Springer
14 years 1 months ago
Improving Data Locality by Chunking
Cache memories were invented to decouple fast processors from slow memories. However, this decoupling is only partial, and many researchers have attempted to improve cache use by p...
Cédric Bastoul, Paul Feautrier
ICPP
1998
IEEE
14 years 21 days ago
A memory-layout oriented run-time technique for locality optimization
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
Yong Yan, Xiaodong Zhang, Zhao Zhang