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PPOPP
2009
ACM
14 years 9 months ago
Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors
Recent advances in polyhedral compilation technology have made it feasible to automatically transform affine sequential loop nests for tiled parallel execution on multi-core proce...
Muthu Manikandan Baskaran, Nagavijayalakshmi Vydya...
MICRO
2005
IEEE
125views Hardware» more  MICRO 2005»
14 years 2 months ago
Improving Region Selection in Dynamic Optimization Systems
The performance of a dynamic optimization system depends heavily on the code it selects to optimize. Many current systems follow the design of HP Dynamo and select a single interp...
David Hiniker, Kim M. Hazelwood, Michael D. Smith
ICNP
2006
IEEE
14 years 2 months ago
Benefit-based Data Caching in Ad Hoc Networks
—Data caching can significantly improve the efficiency of information access in a wireless ad hoc network by reducing the access latency and bandwidth usage. However, designing e...
Bin Tang, Himanshu Gupta, Samir R. Das
GLVLSI
2008
IEEE
112views VLSI» more  GLVLSI 2008»
14 years 2 months ago
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
Maziar Goudarzi, Tohru Ishihara
NCA
2003
IEEE
14 years 1 months ago
Web Proxy Cache Replacement: Do's, Don'ts, and Expectations
Numerous research efforts have produced a large number of algorithms and mechanisms for web proxy caches. In order to build powerful web proxies and understand their performance, ...
Peter Triantafillou, Ioannis Aekaterinidis