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HIPEAC
2011
Springer
12 years 7 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
HPCA
1999
IEEE
13 years 11 months ago
Impulse: Building a Smarter Memory Controller
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
John B. Carter, Wilson C. Hsieh, Leigh Stoller, Ma...
ICS
2010
Tsinghua U.
14 years 4 days ago
Streamlining GPU applications on the fly: thread divergence elimination through runtime thread-data remapping
Because of their tremendous computing power and remarkable cost efficiency, GPUs (graphic processing unit) have quickly emerged as an influential computing platform for a broad ...
Eddy Z. Zhang, Yunlian Jiang, Ziyu Guo, Xipeng She...
SAC
2002
ACM
13 years 7 months ago
On optimal temporal locality of stencil codes
Iterative solvers such as the Jacobi and Gauss-Seidel relaxation methods are important, but time-consuming building blocks of many scientific and engineering applications. The per...
Claudia Leopold
CF
2005
ACM
13 years 9 months ago
A case for a working-set-based memory hierarchy
Modern microprocessor designs continue to obtain impressive performance gains through increasing clock rates and advances in the parallelism obtained via micro-architecture design...
Steve Carr, Soner Önder