332 search results - page 41 / 67 » Cache Write Policies and Performance |
PODC
2005
ACM
14 years 1 months ago
2005
ACM
The obstruction-free Dynamic Software Transactional Memory (DSTM) system of Herlihy et al. allows only one transaction at a time to acquire an object for writing. Should a second ...
ICS
2003
Tsinghua U.
14 years 24 days ago
2003
Tsinghua U.
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
ICPP
1990
IEEE
13 years 11 months ago
1990
IEEE
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
HPDC
2006
IEEE
14 years 1 months ago
2006
IEEE
We develop an adaptive load distribution protocol for logical volume I/O workload in clustered storage systems. It exploits data redundancy among decentralized storage servers to ...
RTSS
2007
IEEE
14 years 1 months ago
2007
IEEE
In multiprocessor systems, the traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers a...