243 search results - page 26 / 49 » Cache miss clustering for banked memory systems |
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
TC
2008
13 years 7 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
IEEEPACT
1998
IEEE
14 years 6 days ago
1998
IEEE
The SGI Origin 2000 is designedto support a wide range of applications and has low local and remote memory latencies. However, it often has a high ratio of remote to local misses....
ISCA
1999
IEEE
14 years 7 days ago
1999
IEEE
By optimizing data layout at run-time, we can potentially enhance the performance of caches by actively creating spatial locality, facilitating prefetching, and avoiding cache con...
JSA
2008
13 years 8 months ago
2008
Conventional snoopy-based chip multiprocessors take an aggressive approach broadcasting snoop requests to all nodes. In addition each node checks all received requests. This appro...