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» Cache modeling in probabilistic execution time analysis
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WMPI
2004
ACM
14 years 2 months ago
Understanding the effects of wrong-path memory references on processor performance
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction al...
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale ...
ISCA
1998
IEEE
139views Hardware» more  ISCA 1998»
14 years 1 months ago
Simultaneous Multithreading: Maximizing On-Chip Parallelism
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
ASPLOS
1994
ACM
14 years 25 days ago
Reducing Branch Costs via Branch Alignment
Several researchers have proposed algorithms for basic block reordering. We call these branch alignment algorithms. The primary emphasis of these algorithms has been on improving ...
Brad Calder, Dirk Grunwald
JPDC
2010
106views more  JPDC 2010»
13 years 7 months ago
Feedback-directed page placement for ccNUMA via hardware-generated memory traces
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
Jaydeep Marathe, Vivek Thakkar, Frank Mueller
NETWORK
2007
234views more  NETWORK 2007»
13 years 8 months ago
Surveillance Wireless Sensor Networks: Deployment Quality Analysis
Surveillance wireless sensor networks are deployed at perimeter or border locations to detect unauthorized intrusions. For deterministic deployment of sensors, the quality of depl...
Ertan Onur, Cem Ersoy, Hakan Deliç, Lale Ak...