1873 search results - page 157 / 375 » Cache performance for multimedia applications |
IEEEPACT
2006
IEEE
14 years 2 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
INFOCOM
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— A TCP-friendly Additive Increase and Multiplicative Decrease (AIMD) protocol is proposed to support timesensitive applications in hybrid wired/wireless networks. By ana...
FPL
2005
Springer
14 years 1 months ago
2005
Springer
At Leiden University, we are developing a design methodology that allows for fast mapping of nested-loop applications (e.g. DSP, Imaging, or MultiMedia) written in a subset of Matl...
PPOPP
2006
ACM
14 years 2 months ago
2006
ACM
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
ISCA
1994
IEEE
14 years 7 days ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...