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ISCA
1995
IEEE
98views Hardware» more  ISCA 1995»
13 years 11 months ago
Instruction Fetching: Coping with Code Bloat
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...
Richard Uhlig, David Nagle, Trevor N. Mudge, Stuar...
IJES
2008
83views more  IJES 2008»
13 years 8 months ago
Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures
Reconfigurable ALU Array (RAA) architectures--representing a popular class of Coarse-grained Reconfigurable Architectures--are gaining in popularity especially for media applicati...
Jong-eun Lee, Kiyoung Choi, Nikil Dutt
GLOBECOM
2006
IEEE
14 years 2 months ago
Price-Sensitive Application Adaptation in Deadline-Based Networks
— In deadline-based networks, the delay performance experienced by real-time data transfer largely depends on traffic deadlines and the load level along the data transfer path. ...
Xiao Huan Liu, Yanni Ellen Liu
JSS
2006
132views more  JSS 2006»
13 years 8 months ago
FMF: Query adaptive melody retrieval system
Recent progress of computer and network technologies makes it possible to store and retrieve a large volume of multimedia data in many applications. In such applications, efficien...
Seungmin Rho, Eenjun Hwang
ISPASS
2008
IEEE
14 years 2 months ago
Pinpointing and Exploiting Opportunities for Enhancing Data Reuse
—The potential for improving the performance of data-intensive scientific programs by enhancing data reuse in cache is substantial because CPUs are significantly faster than me...
Gabriel Marin, John M. Mellor-Crummey