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DFT
2005
IEEE
92views VLSI» more  DFT 2005»
14 years 1 months ago
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lom...
ICPP
1994
IEEE
13 years 11 months ago
Cachier: A Tool for Automatically Inserting CICO Annotations
Shared memory in a parallel computer provides prowith the valuable abstraction of a shared address space--through which any part of a computation can access any datum. Although un...
Trishul M. Chilimbi, James R. Larus
MICRO
1997
IEEE
128views Hardware» more  MICRO 1997»
13 years 12 months ago
Run-Time Spatial Locality Detection and Optimization
As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, lat...
Teresa L. Johnson, Matthew C. Merten, Wen-mei W. H...
ASPLOS
2004
ACM
14 years 1 months ago
Coherence decoupling: making use of incoherence
This paper explores a new technique called coherence decoupling, which breaks a traditional cache coherence protocol into two protocols: a Speculative Cache Lookup (SCL) protocol ...
Jaehyuk Huh, Jichuan Chang, Doug Burger, Gurindar ...
ISCA
1999
IEEE
89views Hardware» more  ISCA 1999»
13 years 12 months ago
Simultaneous Subordinate Microthreading (SSMT)
Current work in Simultaneous Multithreading provides little benefit to programs that aren't partitioned into threads. We propose Simultaneous Subordinate Microthreading (SSMT...
Robert S. Chappell, Jared Stark, Sangwook P. Kim, ...