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IPCCC
2007
IEEE
14 years 1 months ago
Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study
As Chip Multiprocessor (CMP) has become the mainstream in processor architectures, Intel and AMD have introduced their dual-core processors to the PC market. In this paper, perfor...
Lu Peng, Jih-Kwon Peir, Tribuvan K. Prakash, Yen-K...
PVM
2010
Springer
13 years 6 months ago
Locality and Topology Aware Intra-node Communication among Multicore CPUs
A major trend in HPC is the escalation toward manycore, where systems are composed of shared memory nodes featuring numerous processing units. Unfortunately, with scale comes compl...
Teng Ma, George Bosilca, Aurelien Bouteiller, Jack...
IPPS
1999
IEEE
13 years 12 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
ASPDAC
2006
ACM
158views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Analysis of scratch-pad and data-cache performance using statistical methods
— An effectively designed and efficiently used memory hierarchy, composed of scratch-pads or cache, is seen today as the key to obtaining energy and performance gains in data-do...
Javed Absar, Francky Catthoor
CORR
2010
Springer
43views Education» more  CORR 2010»
13 years 7 months ago
Vcache: Caching Dynamic Documents
---- The traditional web caching is currently limited to static documents only. A page generated on the fly from a server side script may have different contents on different acces...
Vipul Goyal, Sugata Sanyal, Dharma P. Agrawal