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DSD
2003
IEEE
14 years 3 months ago
2003
IEEE
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
ISCAS
2005
IEEE
14 years 3 months ago
2005
IEEE
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
WINET
2002
13 years 9 months ago
2002
Abstract. Fair queueing in the wireless domain poses significant challenges due to unique issues in the wireless channel such as locationdependent and bursty channel errors. In thi...
CODES
2008
IEEE
14 years 4 months ago
2008
IEEE
Architectures with software-writable parameters, or configurable architectures, enable runtime reconfiguration of computing platforms to the applications they execute. Such dynami...
TSMC
2010
13 years 4 months ago
2010
We describe a cognitive architecture for creating more robust intelligent systems by executing hybrids of algorithms based on different computational formalisms. The architecture ...