118 search results - page 8 / 24 » Calculation of worst-case execution time for multicore proce... |
CAL
2006
13 years 8 months ago
2006
This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent late...
ET
2002
13 years 8 months ago
2002
Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a prog...
RTAS
1997
IEEE
14 years 29 days ago
1997
IEEE
3rd IEEE Real-time Technology and Applications Symposium (RTAS), June 1997 in Montreal, Canada Cache-partitioning techniques have been invented to make modern processors with an e...
ICCD
1999
IEEE
14 years 1 months ago
1999
IEEE
If a system-on-a-chip (SOC) contains an embedded processor, this paper presents a novel approach for using the processor to aid in testing the other components of the SOC. The bas...
ICIP
2009
IEEE
14 years 9 months ago
2009
IEEE
Rate-distortion (RD) optimized intra-prediction mode selection can lead to significant improvement in coding efficiency in intraframe encoding. However, it would incur considerabl...