Sciweavers

12697 search results - page 2506 / 2540
» Call for Papers
Sort
View
MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
13 years 5 months ago
STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches
Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key...
Dongyuan Zhan, Hong Jiang, Sharad C. Seth
MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
13 years 5 months ago
Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories
Emerging non-volatile memory technologies such as phase change memory (PCM) promise to increase storage system performance by a wide margin relative to both conventional disks and ...
Adrian M. Caulfield, Arup De, Joel Coburn, Todor I...
MICRO
2010
IEEE
270views Hardware» more  MICRO 2010»
13 years 5 months ago
Many-Thread Aware Prefetching Mechanisms for GPGPU Applications
Abstract-- We consider the problem of how to improve memory latency tolerance in massively multithreaded GPGPUs when the thread-level parallelism of an application is not sufficien...
Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim...
OTM
2010
Springer
13 years 5 months ago
On the Expressiveness and Trade-Offs of Large Scale Tuple Stores
Massive-scale distributed computing is a challenge at our doorstep. The current exponential growth of data calls for massive-scale capabilities of storage and processing. This is b...
Ricardo Vilaça, Francisco Cruz, Rui Carlos ...
SECON
2010
IEEE
13 years 5 months ago
Managing TCP Connections in Dynamic Spectrum Access Based Wireless LANs
Wireless LANs have been widely deployed as edge access networks in home/office/commercial buildings, providing connection to the Internet. Therefore, performance of end-toend conne...
Ahwini Kumar, Kang G. Shin
« Prev « First page 2506 / 2540 Last » Next »