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ICCD
2004
IEEE
107views Hardware» more  ICCD 2004»
14 years 6 months ago
Network-on-Chip: The Intelligence is in The Wire
In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at ...
Gérard Mas, Philippe Martin
ETS
2006
IEEE
108views Hardware» more  ETS 2006»
14 years 3 months ago
A DFT Architecture for Asynchronous Networks-on-Chip
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these netwo...
Xuan-Tu Tran, Jean Durupt, François Bertran...
GECCO
2008
Springer
103views Optimization» more  GECCO 2008»
13 years 10 months ago
Empirical investigations on parallel competent genetic algorithms
This paper empirically investigates parallel competent genetic algorithms (cGAs) [4]. cGAs, such as BOA [21], LINCGA [15], D5 -GA [28], can solve GA-difficult problems by automati...
Miwako Tsuji, Masaharu Munetomo, Kiyoshi Akama

Source Code
4838views
15 years 8 months ago
Chan-Vese Image Segmentation
A C++ implementation of Chan-Vese paper "Active Contours Without Edges" image segmentation. The program has command line interface.
Pascal Getreuer
PLDI
2012
ACM
11 years 11 months ago
Dynamic synthesis for relaxed memory models
Modern architectures implement relaxed memory models which may reorder memory operations or execute them non-atomically. Special instructions called memory fences are provided, al...
Feng Liu, Nayden Nedev, Nedyalko Prisadnikov, Mart...