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DSN
2007
IEEE
14 years 3 months ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...
ISCA
2007
IEEE
174views Hardware» more  ISCA 2007»
14 years 3 months ago
An integrated hardware-software approach to flexible transactional memory
There has been considerable recent interest in the support of transactional memory (TM) in both hardware and software. We present an intermediate approach, in which hardware is us...
Arrvindh Shriraman, Michael F. Spear, Hemayet Hoss...
HASE
2007
IEEE
14 years 2 months ago
Simulation Models and Implementation of a Simulator for the Performability Analysis of Electric Power Systems Considering Interd
Electric Power Systems (EPS) become more and more critical for our society, since they provide vital services for the human activities. At the same time, obtaining dependable beha...
Francesco Romani, Silvano Chiaradonna, Felicita Di...
ICS
2007
Tsinghua U.
14 years 2 months ago
GridRod: a dynamic runtime scheduler for grid workflows
Grid Workflows are emerging as practical programming models for solving large e-scientific problems on the Grid. However, it is typically assumed that the workflow components eith...
Shahaan Ayyub, David Abramson
ICS
2007
Tsinghua U.
14 years 2 months ago
Cooperative cache partitioning for chip multiprocessors
This paper presents Cooperative Cache Partitioning (CCP) to allocate cache resources among threads concurrently running on CMPs. Unlike cache partitioning schemes that use a singl...
Jichuan Chang, Gurindar S. Sohi
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