794 search results - page 17 / 159 » Challenges in Parallel Graph Processing |
APPT
2007
Springer
14 years 3 months ago
2007
Springer
It is a great challenge to map network processing tasks to processing resources of advanced network processors, which are heterogeneous and multi-threading multiprocessor System-on...
ICASSP
2008
IEEE
14 years 3 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
IPPS
1998
IEEE
14 years 1 months ago
1998
IEEE
Efficient performance tuning of parallel programs is often hard. In this paper we describe an approach that uses a uni-processor execution of a multithreaded program as reference ...
EDOC
2009
IEEE
14 years 1 months ago
2009
IEEE
A key challenge in devising solutions to a range of problems associated with business process management: process life cycle management, compliance management, enterprise process ...
ICCAD
2006
IEEE
14 years 6 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...